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TWINN: Training-Free Weight-Input Flipping for Mitigating Crossbar Non-Idealities in Binary Neural Network Accelerators

https://doi.org/10.1109/TCSI.2025.3570193

Malhotra, Akul; Gupta, Sumeet Kumar (January 2025, IEEE Transactions on Circuits and Systems I: Regular Papers)

Free, publicly-accessible full text available January 1, 2026
Fault Tolerant In-Memory Computing based on Emerging Technologies for Ultra-Low Precision Edge AI Accelerators

https://doi.org/10.1145/3676536.3697134

Malhotra, Akul; Gupta, Sumeet Kumar (October 2024, ACM)

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Algorithm Hardware Co-Design for ADC-Less Compute In-Memory Accelerator

https://doi.org/10.1109/TCASAI.2024.3495587

Negi, Shubham; Saxena, Utkarsh; Sharma, Deepika; Victor, Jeffry; Ahmed, Imtiaz; Gupta, Sumeet Kumar; Roy, Kaushik (December 2024, IEEE Transactions on Circuits and Systems for Artificial Intelligence)

Free, publicly-accessible full text available December 1, 2025
Material, Device and Circuit-Compatible Modeling of Ferroelectric Devices

https://doi.org/10.1109/MNANO.2023.3278970

Koduru, Revanth; Paul, Tanmoy Kumar; Gupta, Sumeet Kumar (August 2023, IEEE Nanotechnology Magazine)

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Ferroelectric FET Based Coupled-Oscillatory Network for Edge Detection

https://doi.org/10.1109/LED.2021.3117229

Yu, Eunseon; Agrawal, Amogh; Zheng, Dongqi; Si, Mengwei; Koo, Minsuk; Ye, Peide D.; Gupta, Sumeet Kumar; Roy, Kaushik (November 2021, IEEE Electron Device Letters)

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Integrated CAM-RAM Functionality using Ferroelectric FETs

https://doi.org/10.1109/ISQED48828.2020.9136998

George, Sumitha; Jao, Nicolas; Ramanathan, Akshay Krishna; Li, Xueqing; Gupta, Sumeet Kumar; Sampson, John; Narayanan, Vijaykrishnan (March 2020, 2020 21st International Symposium on Quality Electronic Design (ISQED))

This work proposes a new Ferroelectric FET (FeFET) based Ternary Content Addressable Memory (TCAM) with features of integrated search and read operations (along with write), which we refer to as TCAM-RAM. The proposed memory exploits the unique features of the emerging FeFET technology, such as 3-terminal device design, storage in the gate stack, etc., to achieve the proposed functionality. We also introduce Approximate CAM-RAM, which can quantize the bit vector similarity. All the proposed designs operate without negative voltages. We describe both NAND and NOR variants of CAM design. Our CAM design provides 31% area improvement over the previous FeFET 6T CAM design.
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